Classic digital logic design utilizes Boolean mathematical expressions to build digital logic circuits since there is a one-to-one correspondence between such expressions and their digital representation. Boolean identities can be utilized to reduce these expressions, and thus minimize both combinational and sequential circuit complexity (e.g., the number of transistors used in the circuit). Other tools such as DeMorgan's Theorem and truth tables can also be employed to simplify the expressions and thereby minimize the number of circuits to implement a given digital logic design. Such classical approaches generally provide a logic representation that minimizes the number of circuits yet these approaches may not always provide the best solution for mitigating circuitry depending on the nature of the underlying logic application.